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industrial temperature range IDT74ALVCH16903 3.3v cmos 12-bit universal bus driver with parity checker 1 january 2004 industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. ? 2004 integrated device technology, inc. dsc-4911/2 features: ? 0.5 micron cmos technology ? typical t sk(o) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 3.3v 0.3v, normal range ?v cc = 2.7v to 3.6v, extended range ?v cc = 2.5v 0.2v ? cmos power levels (0.4 w typ. static) ? rail-to-rail output swing for increased noise margin ? available in ssop and tssop packages applications: ? 3.3v high speed systems ? 3.3v and lower voltage computing systems drive features: ? high output drivers: 24ma ? suitable for heavy loads IDT74ALVCH16903 3.3v cmos 12-bit universal bus driver with parity checker, dual 3-state outputs and bus-hold description: this 12-bit universal bus driver is built using advanced dual metal cmos technology. this device has dual outputs and can operate as a buffer or an edge-triggered register. in both modes, parity is checked on apar, which arrives one cycle after the data to which it applies. the yerr output, which is produced one cycle after apar, is open drain. mode selects one of the two data paths. when mode is low, the device operates as an edge-triggered register. on the positive transition of the clock (clk) input and when the clock-enable ( clken ) input is low, data setup at the a inputs is stored in the internal registers. on the positive transition of clk and when clken is high, only data setup at the 9a-12a inputs is stored in their internal registers. when mode is high, the device operates as a buffer and data at the a inputs passes directly to the outputs. the 11a/ yerren serves a dual purpose; it acts as a normal data bit and also enables yerr data to be clocked into the yerr output register. when used as a single device, parity output enable ( paroe ) must be tied high; when parity input/output (pari/o) is low, even parity is selected and when pari/o is high, odd parity is selected. when used in pairs and paroe is low, the parity sum is output on pari/o for cascading to the second alvch16903. when used in pairs and paroe is high, pari/o accepts a partial parity sum from the first alvch16903. a buffered output-enable ( oe ) input can be used to place the 24 outputs and yerr in either a normal logic state (high or low logic levels) or a high-impedance state. in the high-impedance state, the outputs neither load nor drive the bus lines significantly. the high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. the alvch16903 has been designed with a 24ma output driver. this driver is capable of driving a moderate to heavy load while maintaining speed performance. the alvch16903 has ?bus-hold? which retains the inputs? last state whenever the input bus goes to a high-impedance. this prevents floating inputs and eliminates the need for pull-up/down resistors. symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +4.6 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v (outputs only) t stg storage temperature ?65 to +150 c i out dc output current ?50 to +50 ma i ik continuous clamp current, 50 ma v i < 0 or v i > v cc i ok continuous clamp current, v o < 0 ?50 ma i cc continuous current through each 100 ma i ss v cc or gnd absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminals. 3. this value is limited to 4.6v maximum. note: 1. as applicable to the device type. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 5 7 pf c out output capacitance v out = 0v 7 9 pf c out i/o port capacitance v in = 0v 7 9 pf capacitance (t a = +25c, f = 1.0mhz)
industrial temperature range 2 IDT74ALVCH16903 3.3v cmos 12-bit universal bus driver with parity checker functional block diagram oe 1 29 28 mode 33 clk 56 1a-12a, apar clken 13 13 (9a-12a, apar) (1a-11a/yerren, apar) paroe (1a-12a) 12 flip flop flip flop parity check xor d q d q d q d q (1a-10a) 10 11 apar apar (11a/yerren) yerr pari/o 30 12 12 36 12 1y2-12y2 1y1-12y1 (1a-8a) 8 13 13 5 5 function table (1) inputs outputs oe mode clken clk a 1yx-8yx 9yx-12yx lll hh h lll ll l llh hy (2) h llh ly (2) l lhxxh h h lhxxl l l hxxxx z z notes: 1. h = high voltage level l = low voltage level x = don?t care = low-to-high transition 2. output level before the indicated steady-state conditions were established. parity function table (1) inputs output oe paroe (2) 11a/ pari/o of inputs apar yerr yerren (3) 1a-10a= h l h l l 0, 2, 4, 6, 8, 10 l h l h l l 1, 3, 5, 7, 9 l l l h l l 0, 2, 4, 6, 8, 10 h l l h l l 1, 3, 5, 7, 9 h h l h l h 0, 2, 4, 6, 8, 10 l l l h l h 1, 3, 5, 7, 9 l h l h l h 0, 2, 4, 6, 8, 10 h h l h l h 1, 3, 5, 7, 9 h l hx x x x xh lx h x x xh notes: 1. h = high voltage level l = low voltage level x = don?t care 2. when used as a single device, paroe must be tied high. 3. valid after appropriate number of clock pulses have set internal register.
industrial temperature range IDT74ALVCH16903 3.3v cmos 12-bit universal bus driver with parity checker 3 ssop/ tssop top view pin configuration gnd gnd gnd 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 47 46 45 44 43 42 41 40 39 38 37 36 35 34 48 49 50 51 52 53 54 55 56 1 gnd gnd clk 1a 11a/yerren oe 1y 1 1y 2 2y 1 2y 2 3y 1 3y 2 4y 1 4y 2 5y 1 5y 2 6y 1 6y 2 7y 1 7y 2 8y 1 8y 2 9y 1 11y 1 11y 2 2a 3a 4a 12a 12y 1 12y 2 5a 6a 7a apar 8a yerr v cc 9a gnd v cc v cc v cc 24 33 gnd 25 27 30 9y 2 10y 1 mode 10a pari/o gnd 10y 2 26 31 32 paroe clken 29 28 pari/o function table (1) inputs output paroe of inputs apar pari/o 1a-10a = h l 0, 2, 4, 6, 8,10 l l l 1, 3, 5, 7, 9 l h l 0, 2, 4, 6, 8, 10 h h l 1, 3, 5, 7, 9 h l hxxz note: 1. this table applies to the first device of a cascaded pair of alvch16903 devices. note: 1. these pins have "bus-hold". all other pins are standard inputs, outputs, or i/os. pin names i/o description 1a-12a i data inputs (1) 1y1-12y2 o 3-state data outputs clk i clock input clken i clock enable input (active low) mode i select pin yerren i error signal output enable (active low) paroe i parity output enable (active low) pari/o i/o parity input/output yerr o error signal (open drain) oe i output enable input (active low) apar i parity input pin description
industrial temperature range 4 IDT74ALVCH16903 3.3v cmos 12-bit universal bus driver with parity checker symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 ? ? v v cc = 2.7v to 3.6v 2 ? ? v il input low voltage level v cc = 2.3v to 2.7v ? ? 0.7 v v cc = 2.7v to 3.6v ? ? 0.8 i ih input high current v cc = 3.6v v i = v cc ?? 5a i il input low current v cc = 3.6v v i = gnd ? ? 5 i ozh high impedance output current v cc = 3.6v v o = v cc ? ? 10 a i ozl (3-state output pins) v o = gnd ? ? 10 a i oh yerr output v cc = 0v to 3.6v v o = v cc ? ? 10 a i oz (2) high impedance output current v cc = 3.6v v o = v cc or gnd ? ? 10 a v ik clamp diode voltage v cc = 2.3v, i in = ? 18ma ? ? 0.7 ? 1.2 v v h input hysteresis v cc = 3.3v ? 100 ? mv i ccl i cch quiescent power supply current v cc = 3.6v, v in = gnd or v cc ? 0.1 40 a i ccz ? i cc quiescent power supply one input at v cc ? 0.6v, other inputs at v cc or gnd ? ? 750 a current variation ci control inputs v cc = 3.3v v i = v cc or gnd ? 5.5 ? pf data inputs ? 5.5 ? co yerr output v cc = 3.3v v o = v cc or gnd ? 5 ? pf data outputs ?6 ? cio pari/o v cc = 3.3v v o = v cc or gnd ? 7 ? pf dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = ?40c to +85c notes: 1. typical values are at v cc = 3.3v, +25c ambient. 2. for i/o ports, the parameter i oz includes the input leakage current. bus-hold characteristics symbol parameter (1) test conditions min. typ. (2) max. unit i bhh bus-hold input sustain current v cc = 3v v i = 2v ? 75 ? ? a i bhl v i = 0.8v 75 ? ? i bhh bus-hold input sustain current v cc = 2.3v v i = 1.7v ? 45 ? ? a i bhl v i = 0.7v 45 ? ? i bhho bus-hold input overdrive current v cc = 3.6v v i = 0 to 3.6v ? ? 500 a i bhlo notes: 1. pins with bus-hold are identified in the pin description. 2. typical values are at v cc = 3.3v, +25c ambient.
industrial temperature range IDT74ALVCH16903 3.3v cmos 12-bit universal bus driver with parity checker 5 output drive characteristics, xyx ports symbol parameter test conditions (1) min. max. unit v cc = 2.3v to 3.6v i oh = ? 0.1ma v cc ? 0.2 ? v cc = 2.3v i oh = ? 6ma, v ih = 1.7v 2 ? v oh output high voltage v cc = 2.3v i oh = ? 12ma, v ih = 1.7v 1.7 ? v v cc = 2.7v i oh = ? 12ma, v ih = 2v 2.2 ? v cc = 3v 2.4 ? v cc = 3v i oh = ? 24ma, v ih = 2v 2 ? v cc = 2.3v to 3.6v i ol = 0.1ma ? 0.2 v cc = 2.3v i ol = 6ma, v il = 0.7v ? 0.4 v ol output low voltage i ol = 12ma, v il = 0.7v ? 0.7 v v cc = 2.7v i ol = 12ma, v il = 0.8v ? 0.4 v cc = 3v i ol = 24ma, v il = 0.8v ? 0.55 v cc = 2.3v y port ? ? 12 i oh high-level output current v cc = 2.7v ? ? 12 ma v cc = 3v pari/o ? ? 12 y port ? ? 24 v cc = 2.3v y port ? 12 v cc = 2.7v ? 12 i ol low-level output current pari/o ? 12 ma v cc = 3v y port ? 24 yerr output ? 24 note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriat e v cc range. t a = ? 40c to + 85c. output drive characteristics for yerr and pari/o symbol parameter test conditions (1) min. max. unit v oh pari/o v cc = 3v i oh = ? 12ma, v ih = 2v 2 ? v v ol pari/o v cc = 3v i ol = 12ma, v il = 0.8v ? 0.55 v v ol yerr output only v cc = 3v i ol = 24ma ? 0.5 v note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriat e v cc range. t a = ? 40c to + 85c.
industrial temperature range 6 IDT74ALVCH16903 3.3v cmos 12-bit universal bus driver with parity checker operating characteristics for buffer mode, t a = 25c v cc = 2.5v 0.2v v cc = 3.3v 0.3v symbol parameter test conditions typical typical unit c pd power dissipation capacitance outputs enabled c l = 0pf, f = 10mhz 57.5 65 pf c pd power dissipation capacitance outputs disabled 15 17.5 operating characteristics for register mode, t a = 25c v cc = 2.5v 0.2v v cc = 3.3v 0.3v symbol parameter test conditions typical typical unit c pd power dissipation capacitance outputs enabled c l = 0pf, f = 10mhz 57 87.5 pf c pd power dissipation capacitance outputs disabled 16.5 34 simultaneous switching characteristics (1) parameter from to v cc = 2.5v 0.2v v cc = 2.7v v cc = 3.3v 0.3v (input) (output) min. max. min. max. min. max. unit t plh register mode clk y 1.8 6.5 6.1 1.8 5 ns t phl 1.4 5.9 5.1 1.7 4.5 note: 1. all outputs switching.
industrial temperature range IDT74ALVCH16903 3.3v cmos 12-bit universal bus driver with parity checker 7 v cc = 2.5v 0.2v v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. min. max. unit f max 125 ? 125 ? 125 ? m h z t plh propagation delay, buffer mode 1 4.4 ? 4.2 1.1 3.8 ns t phl xax to xyx t plh propagation delay, both modes 1 5.7 ? 4.9 1.4 4.4 ns t phl clk to yerr t plh propagation delay, both modes 1.2 8.6 ? 7.9 1.7 6.6 ns t phl clk to pari/o t plh propagation delay, both modes 1 6.8 ? 5.2 1.3 4.5 ns t phl clk to pari/o t plh propagation delay, both modes 1 5.9 ? 5.8 1.3 4.9 ns t phl mode to xyx t plh propagation delay, register mode 1 6.1 ? 5.5 1.2 4.8 ns t phl clk to xyx 1 5.9 ? 4.9 1.2 4.6 t plh propagation delay, both modes 1 3.6 ? 4.2 1.9 4 ns oe to yerr t phl propagation delay, both modes 1.2 5.1 ? 4.9 1.5 4.2 ns oe to yerr t pzh output enable time, both modes 1.1 6.5 ? 6.4 1.4 5.4 ns t pzl oe to xyx t pzh output enable time, both modes 1 5.6 ? 6 1 4.8 ns t pzl paroe to pari/o t phz output disable time, both modes 1 6.4 ? 5.2 1.7 5 ns t plz oe to xyx t phz output disable time, both modes 1 3.2 ? 3.8 1.2 3.8 ns t plz paroe to pari/o t su set-up time, register mode, 1a-12a before clk 1.7 ? 1.9 ? 1.45 ? ns t su set-up time, buffer mode, 1a to 10a before clk 5.9 ? 5.2 ? 4.4 ? ns t su set-up time, register mode, apar before clk 1.2 ? 1.5 ? 1.3 ? ns t su set-up time, buffer mode, apar before clk 4.6 ? 3.6 ? 3.1 ? ns t su set-up time, both modes, pari/o before clk 2.4 ? 2 ? 1.7 ? ns t su set-up time, buffer mode, 11a/ yerren before clk 2 ? 1.9 ? 1.6 ? ns t su set-up time, register mode, clken before clk 2.5 ? 2.6 ? 2.2 ? ns t h hold time, register mode, 1a-12a after clk 0.4 ? 0.25 ? 0.55 ? ns t h hold time, buffer mode, 1a-10a after clk 0.25 ? 0.25 ? 0.25 ? ns t h hold time, register mode, apar after clk 0.7 ? 0.4 ? 0.7 ? ns t h hold time, buffer mode, apar after clk 0.25 ? 0.25 ? 0.25 ? ns t h hold time, register mode, pari/o after clk 0.25 ? 0.25 ? 0.4 ? ns t h hold time, buffer mode, pari/o after clk 0.25 ? 0.25 ? 0.5 ? ns t h hold time, buffer mode, 11a/ yerren after clk 0.25 ? 0.25 ? 0.4 ? ns t h hold time, register mode, clken after clk 0.25 ? 0.5 ? 0.4 ? ns t w pulse width, clk 3?3?3? ns t sk(o) output skew (2) ? ????500 ps switching characteristics (1) notes: 1. see test circuits and waveforms. t a = ? 40c to + 85c. 2 skew between any two outputs of the same package and switching in the same direction.
industrial temperature range 8 IDT74ALVCH16903 3.3v cmos 12-bit universal bus driver with parity checker open v load gnd v cc pulse generator d.u.t. 500 ? 500 ? c l r t v in v out (1, 2) alvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 alvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t alvc link data input 0v 0v 0v 0v t rem timing input synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t alvc link asynchronous control low-high-low pulse high-low-high pulse v t t w v t alvc link control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v hz alvc link test circuits and waveforms propagation delay test circuit for all outputs enable and disable times set-up, hold, and release times notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 1.0mhz; t f 2ns; t r 2ns. output skew - t sk ( x ) pulse width note: 1. diagram shown for input control enable-low and input control disable-high. symbol v cc (1) = 3.3v0.3v v cc (1) = 2.7v v cc (2) = 2.5v0.2v unit v load 6 6 2 x vcc v v ih 2.7 2.7 vcc v v t 1.5 1.5 vcc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf test conditions switch position test switch open drain disable low v load enable low disable high gnd enable high all other tests open
industrial temperature range IDT74ALVCH16903 3.3v cmos 12-bit universal bus driver with parity checker 9 0v input 2.7v t w 1.5v 1.5v 0v data input 2.7v t su 1.5v 1.5v timing input 1.5v 0v 2.7v t h 0v v ol output v oh 1.5v t phl input t plh open gnd 500 ? 500 ? c l = 30 pf (see note 1) s1 6v from output under test test s1 t pd t plz /t pzl t phz /t pzh open 6v gnd yerr s1 t phl (see note 8) t plh (see note 9) 6v 6v output control (low-level enabling) t plz 0v t pzh output waveform 2 s1 at gnd (see note 2) 1.5v 0v v oh t pzl 1.5v 3v 2.7v v ol v oh -0.3v 1.5v 1.5v v ol+ 0.3v t phz output waveform 1 s1 at 6v (see note 2) 1.5v 2.7v 1.5v 1.5v parameter measurement information v cc = 2.7v and 3.3v 0.3v notes: 1. c l includes probe and jig capacitance. 2. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , tr 2 ns, tf 2 ns. 4. the outputs are measured one at a time with one transition per measurement. 5. t plz and t phz are the same as t dis . 6. t pzl and t pzh are the same as t en . 7. t plh and t phl are the same as t pd . 8. t phl is measured at 1.5v. 9. t plh is measured at v ol +0.3v. load circuit voltage waveforms pulse duration voltage waveforms setup and hold times voltage waveforms enable and disabletimes voltage waveforms propagation delay times
industrial temperature range 10 IDT74ALVCH16903 3.3v cmos 12-bit universal bus driver with parity checker 0v v oh v ol t plh t phl output 2.7v 1.5v 1.5v 1.5v 1.5v input load circuit and voltage waveforms v cc = 2.7v and 3.3v 0.3v test point cl = 0.6 pf (see note 1) cl = 0.6 pf (see note 1) pari/o of second alvch16903 z o = 52 ? t d = 63 ps from output under test pari/o note: 1. c l includes probe and jig capacitance. pari/o load circuit
industrial temperature range IDT74ALVCH16903 3.3v cmos 12-bit universal bus driver with parity checker 11 0v input v cc t w v cc/2 v cc/2 0v data input v cc t su v cc/2 v cc/2 timing input v cc/2 0v v cc t h 0v v ol output v cc /2 v cc /2 v cc /2 v oh v cc /2 v cc t phl input t plh open gnd 500 ? 500 ? c l = 30 pf (see note 1) s1 2 x v cc from output under test test s1 t pd t plz /t pzl t phz /t pzh open 2 x v cc gnd yerr s1 t phl (see note 8) t plh (see note 9) 2 x v cc 2 x v cc input control (low-level enabling) t plz 0v t pzh output waveform 2 s1 at gnd (see note 2) v cc /2 0v v oh t pzl vcc /2 v cc v cc v ol v oh -0.15v v cc /2 vcc /2 v ol+ 0.15v t phz output waveform 1 s1 at 2xvcc (see note 2) parameter measurement information v cc = 2.5v 0.2v notes: 1. c l includes probe and jig capacitance. 2. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , tr 2 ns, tf 2 ns. 4. the outputs are measured one at a time with one transition per measurement. 5. t plz and t phz are the same as t dis . 6. t pzl and t pzh are the same as t en . 7. t plh and t phl are the same as t pd . 8. t phl is measured at v cc /2. 9. t plh is measured at v ol + 0.15v. load circuit voltage waveforms pulse duration voltage waveforms setup and hold times voltage waveforms enable and disabletimes voltage waveforms propagation delay times
industrial temperature range 12 IDT74ALVCH16903 3.3v cmos 12-bit universal bus driver with parity checker 0v v ol output v cc /2 v cc /2 v cc /2 v oh v cc /2 v cc t phl input t plh r l = 10 ? c l = 30 pf (see note 1) from output under test 0v v ol output v cc /2 v cc /2 v cc /2 v oh v cc /2 v cc t phl input t plh test point test point cl = 0.6 pf (see note 1) cl = 0.6 pf (see note 1) pari/o of second alvch16903 z o = 52 ? t d = 63 ps from output under test pari/o parameter measurement information v cc = 2.5v 0.2v load circuit load circuit notes: 1. c l includes probe and jig capacitance. 2. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, zo = 50 ? , tr 2 ns, tf 2ns. 3. t plh and t phl are the same as t pd . voltage waveforms propagation delay times voltage waveforms propagation delay times notes: 1. c l includes probe and jig capacitance. 2. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, zo = 50 ? , tr 2 ns, tf 2ns.
industrial temperature range IDT74ALVCH16903 3.3v cmos 12-bit universal bus driver with parity checker 13 ordering information corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com idt xx alvc xxx xx package device type temp. range pv pa 16 74 shrink small outline package thin shrink small outline package 12-bit universal bus driver with parity checker -40c to +85c x xxx family bus-hold 903 double-density, 24ma bus-hold h

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